{ "schema": "lumencore.synthetic_resistor_screen.v1", "claim_level": "internal_synthetic_screening_only", "promotion_gate_passed": false, "run_date": "2026-10-04", "purpose": "Compare ideal DC resistor-network transport and topological fault tolerance under declared normalized constraints.", "primary_metric": "mean_effective_conductance (higher within the controlled group only; all 2016 terminal pairs equally weighted)", "reference_baseline": "square_grid", "normalization": { "node_count": 64, "diameter": 1, "material_budget": 1, "resistivity": 1, "uniform_cross_section_per_graph": true, "terminal_pairs": "all unordered pairs, equal weights", "boundary": "open boundaries, pairwise source and sink; all other nodes obey Kirchhoff current conservation" }, "seeds": { "randomized_tree": 20261005, "all_other_graphs": "deterministic, no random numbers" }, "metric_units": { "diameter": "D", "total_wire_length": "D", "uniform_cross_section": "V/D", "material_budget": "V", "mean_effective_conductance": "V/(rho*D^2); normalized dimensionless when D=V=rho=1", "mean_effective_resistance": "rho*D^2/V", "mean_path_stretch": "dimensionless", "worst_path_stretch": "dimensionless", "failure_metrics": "fractions of exhaustive single-edge deletions or node pairs" }, "limitations": [ "No time, frequency, capacitance, inductance, dielectric loss, impedance matching, bandwidth, attenuation, signal-to-noise, Maxwell equations, or fluid dynamics are modeled.", "Adding wire lowers every edge cross-section at fixed volume; conductance need not improve. Edge count is disclosed, not held fixed.", "Honeycomb and sunflower use different terminal coordinates and boundary aspect ratios: exploratory embedding comparison only; do not pool or rank as controlled topology gains.", "Only one deterministic layout per family and one fixed random control seed. This is not the frozen multi-fold promotion gate, uncertainty analysis, or experimental validation.", "Loop-augmented tree is a designed heuristic, not a validated fungal or slime-mold growth model.", "Wire intersections away from named nodes do not create junctions; edge overlaps, finite conductor width, contact resistance, junction volume, and manufacturability are ignored.", "Fault metric measures connectivity only; it does not measure post-failure conductance, targeted node damage, correlated failures, healing, or physical device reliability.", "Uniform cross-section is a policy choice; no optimal radius allocation, Murray-law hydraulic model, or equal compute budget for topology construction is claimed.", "Metric choice and graph definitions were fixed before this run, but there is no independent preregistration or holdout dataset. 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